Version: 2025/02/20

Table of Contents:

1. About SiFive Freedom
2. Freedom Build (Chisel→Verilog)
3. Arty-A7 Bitstream Creation

1. About SiFive Freedom

1.1. Overview of SiFive Freedom

• • An open-source implementation platform based on the Rocket chip.
• • Publicly available at:
• • https://github.com/sifive/freedom
• • Code freeze on March 1, 2021 (no maintenance since then).
• • Two platforms:
• • Freedom E300: 32-bit, compatible with RTOS and Arty A7.
• • Freedom U500: 64-bit for Linux.

• • Currently migrating to chipyard.

2. Freedom Build (Chisel→Verilog)

2.1. Current Challenges and Countermeasures for Building Freedom

• • Due to the code freeze, an older environment is required.
• • Links to non-existent URLs for submodules.

• • Prepare repositories and tools on the host side and build in a container.
• • Share the project folder between the host and the container.

2.2. On the Use of Docker

• • OS-level virtualization using container virtualization.

Using the official ubuntu image as is

Building and using Dockerfile

2.3. Procedure for Verilog Generation

2.4. Getting Freedom Files（１）

git clone https://github.com/sifive/freedom.git

cd freedom
git submodule update --init --recursive

git submodule status --recursive

-65cc4d2748a2c2e6f2... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/dtc
-87eea99e443b389c97... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/pixman
-e3d05727a074619fc1... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/SLOF
-04186319181298083e... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/ipxe
-c5542f226c0d3d61e7... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/openbios
-c559da7c8eec5e45ef... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/openhackware
+99d9b4dcf27d7fbcba... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/qemu-palcode (heads/master)
-e2fc41e24ee0ada60f... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/seabios
-23d474943dcd55d055... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/sgabios
-2072e7262965bb48d7... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/u-boot
-19ea12c230ded95928... rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/roms/vgabios

2.4. Getting Freedom Files（２）

rocket-chip/riscv-tools/riscv-gnu-toolchain/riscv-qemu/.gitmodules

git submodule sync –recursive
git submodule update --init --recursive

2.4. Getting Freedom Files（３）

rocket-chip/firrtl/project/plugins.sbt
rocket-chip/chisel3/project/plugins.sbt

Delete the first line below (Reason: An error occurs because the URL is invalid)

resolvers += Resolver.url("scalasbt", new
URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases"))
(Resolver.ivyStylePatterns)

resolvers += Classpaths.sbtPluginReleases

resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"

addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0")

addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")

...

2.5. Getting tools（１）

2.5. Getting the tools (2) Identifying the sbt version

2.5. Getting the tools (3) Getting sbt

• • Add the sbt repository to the apt source list
• • Download a specific version of sbt

sudo apt-get update
echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | ¥
sudo -H gpg --no-default-keyring --keyring gnupg-ring:/etc/apt/trusted.gpg.d/scalasbt-release.gpg --import
sudo chmod 644 /etc/apt/trusted.gpg.d/scalasbt-release.gpg
sudo apt-get update

apt-get download sbt=1.2.1

2.5. Getting the tool (4) Getting verilator

• • ※ Changed from the procedure described in README.md

git clone https://github.com/verilator/verilator

cd verilator
git checkout -b verilator_3_922 v3.922

2.5. Getting the tools (5) Getting the RISC-V toolchain

• • README.md does not specify the specific version
• • Get the files from the following SiFive website

https://github.com/sifive/freedom-tools/releases

wget https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12/riscv64-
unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz

tar xzf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linuxubuntu14.
tar.gz –c <Directories accessible from container>

2.6. Starting the container (1) Prerequisites

2.6. Starting the container (2) Starting

cd /home/<user>/<project>
docker run –it –v $PWD/$PWD ubuntu:18.04 /bin/bash

2.7. Container setup (1) Setup with root

apt-get update
apt-get install -y sudo ca-certificates curl wget locales

groupadd -g <gid> <group>
useradd -g<gid> -m -s /bin/bash -u <uid> <user>
usermod -G sudo <user>
echo '%sudo ALL=(ALL) NOPASSWD:ALL' >> /etc/sudoers

su <user>

2.7. Container setup (2)

cd <sbt download location>
sudo dpkg –i sbt_1.2.1_all.deb

sudo apt-get install –y openjdk-11-jdk git scala device-tree-compiler
sudo apt-get install -y autoconf automake autotools-dev bison flex build-essential
sudo apt-get install -y bc gawk texinfo gperf libtool patchutils python pkg-config
sudo apt-get install -y libmpc-dev libmpfr-dev libgmp-dev zlib1g-dev libexpat-dev

2.7. Container setup (3)

cd <Verilator local repository>
unset VERILATOR_ROOT
autoconf
./configure
make
sudo make install

cd <Parent directory of RISC-V toolchain>
export RISCV=$PWD/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14
PATH=$PATH:$RISCV/bin

2.8. Build execution

• • Run sbt alone before make

cd /home/<user>/<project>/freedom
sbt
sbt:freedom> exit

make -f Makefile.e300artydevkit verilog

3. Arty-A7 Bitstream Creation

3.1. Bitstream Creation Approach

• • Change settings on the host side
• • Build with containers until using vivado
• • vivado runs on the host

3.2. Changing board settings

diff --git a/Makefile.e300artydevkit b/Makefile.e300artydevkit
index 110c08a..3476a60 100644
--- a/Makefile.e300artydevkit
+++ b/Makefile.e300artydevkit
@@ -6,7 +6,7 @@ MODEL := E300ArtyDevKitFPGAChip
PROJECT := sifive.freedom.everywhere.e300artydevkit
export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
export CONFIG := E300ArtyDevKitConfig
-export BOARD := arty
+export BOARD := arty_a7_100

diff --git a/xilinx/arty_a7_100/tcl/board.tcl b/xilinx/arty_a7_100/tcl/board.tcl
index 70635da..552d70f 100644
--- a/xilinx/arty_a7_100/tcl/board.tcl
+++ b/xilinx/arty_a7_100/tcl/board.tcl
@@ -1,5 +1,5 @@
# See LICENSE for license details.
set name {arty-a7-100}
set part_fpga {xc7a100ticsg324-1L}
-set part_board {digilentinc.com:arty-a7-100:part0:1.0}
+set part_board {digilentinc.com:arty-a7-100:part0:1.1}

3.3. romgen build

make -f Makefile.e300artydevkit romgen

3.4. Checking and adding Vivado board settings (1)

vivado –mode tcl

xhub::refresh_catalog [xhub::get_xstores xilinx_board_store]
get_port_parts
...
digilentinc.com:arty-a7-100:part0:1.0 digilentinc.com:arty-a7-100:part0:1.1 ...

If you do not have arty-a7-100 -> Add this

xhub::install [xhub::get_xitems "*arty-a7*"]

3.4. Checking and adding Vivado board settings (2)

The added board information is installed in the home directory, so it needs to be set when vivado starts

echo ¥
  “set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]” ¥
  >>~/.Xilinx/Vivado/2024.1/Vivado_init.tcl

Restart vivado and execute the following

get_port_parts

3.5. mcs build

• • Confirm that the mcs file is generated

make -f Makefile.e300artydevkit mcs